1. Field of the Invention
The present invention relates to a shaving or shearing blade utilized in dressing sites in solder joint chip technologies by removing excess solder without the use of heat or a copper block wicking process; to a method of implementing the dressing procedure, and to the use of the shaving or shearing blade. In essence, any solder debris resulting from the solder shaving process as implemented by the shaving or shearing blade is removed through the intermediary of a vacuum arrangement which is located as an integral structure in the shaving blade so as to inhibit the potential formation of electrical shorts or causing solder damage in subsequent replacement chip joins or other assembly operations.
The techniques of removing components from multichip modules, including thermal conduction modules and the like, have been well developed in the technology. Although several methods for removing components are currently in existence, site dress utilizing the wicking action of a copper block has always been employed in order to remove excess solder so as to enable a new component to be placed on the site. However, when joining the component to a new chip site, the contact non-wet failure rate is quite considerable. Copper block site dress processes are also involved in their implementation and somewhat difficult to implement. Thus, once a component is removed from the multichip module, the component must be inspected for any bottom layer metallurgy tear-out or similar condition because a copper block will not properly dress the site held up by any debris, such as particles or other debris caused by solder removal. The copper block(s) is normally located on the site and is heated to reflow temperatures to wick any excess solder. The copper block frequently requires a time-consuming cleaning action prior to reuse. The copper block can be expensive to produce and pre-tinning and flux may be required.
Much of the currently available component-replacement technology, surface mount (SMT) and pin-in-hole (PIH) is not directly extendable to replacing individual area-array solder ball flip chips (SBFC) on multichip modules. Flip-chip replacement offers some unique challenges in addition to those encountered in the removing SMT or PIH components. In general, SBFC require a more sophisticated replacement technology capable of tight parametric control. Conventional chip attachments, in essence, such as wire bond or tape automated bonds (TAB), do not readily lend themselves to chip replacement, although some progress has been recently made in this technology.
2. Discussion of the Prior Art
Several chip removal and ref lux-techniques and their attributes have been presented and extensively discussed in an article entitled "An Overview of Flip-chip Replacement Technology on MLC Multichip Modules"; The International Journal of Microcircuits and Electronic Packaging; Volume 15, Number 3, Third Quarter 1992; pages 113-126. Flip-chip replacement can be tailored to satisfy specific conditions and situations. For example, removal may be achieved by mechanical means such as by the application of torques or ultrasound, or with the aid of a suitable heat source or sources, as described in the above-reference article. Mechanical methods are preferred, being both simple and capable of higher throughput. However, constraints such as proximity to other surface features, chip footprint, or the like, often dictate the replacement methods. Also considered have been module constraints such as anisotropic thermal conductivity, mass, etc. and their effects. It will be demonstrated that with the present invention, even under difficult conditions; for instance, high degree of constraints, flip-chips can be individually removed and rejoined successfully.
After chip removal, residual solder left on substrate pads is removed. This procedure prevents shorts between adjacent pads due to solder accumulation at sites which experience multiple replacements. So-called site dressing is also necessary to assure joint integrity by maintaining a solder volume which optimizes thermal fatigue life.
Various methods and tools have been utilized in the technology to dress sites or otherwise treat locations to remove debris or the like.
Nolan et al. U.S. Pat. No. 5,216,803 discloses the removal of remnant wire bonds from tape automated bonded (TAB) chips, and as such does not address specific requirements encountered in the removal of residual solder on various sites; for example, such as so-called C4 or controlled collapse chip connections which are the frequent interconnections of individual area array solder ball flip chips (SBFC) located on multichip modules.
Venutolo U.S. Pat. No. 4,954,453 discloses a chip removal method utilizing heat in order to break the solder interconnect at a uniform height. However, the patent does not address itself to the removal of residual solder or debris following the removal operation for a chip.
Brown et al. U.S. Pat. No. 4,768,698 discloses an X-Y table providing a quick shear option which is adapted to remove components from printed circuit boards which have been heated through the intermediary of a hot air nozzle.
Jensen et al. U.S. Pat. No. 4,152,172 discloses the vinyl scrubbing of input/output terminals of semiconductor elements of a semiconductor waver for the removal of oxides.